//////////////////////////////////////////////////
////file: count.v
////Author: Qyw 
//////////////////////////////////////////////////////

module count(//input
			clk_1m,
			rst_n,
			oe,
			active,
			active_check,
			cnt_clr,
			chk_cnt_clr,
			dec_en,
			//output
			car_cnt,
			car_L2H
				);

input		clk_1m,		//1M clock signal
			rst_n,		//async rst singal
			oe,			//oe signal
			cnt_clr,	//clear carrier cnt
			chk_cnt_clr, //clear carrier cnt in check stage;
			active,		//active start to count the carrier
			dec_en,		//decode enable
			active_check; //in check mode the active signal
output	[5:0] car_cnt;	//car_cnt signal
output		   car_L2H;

reg			[8:0]	cnt;
reg			[3:0]	bits;

assign car_cnt = cnt[8:3];
assign car_L2H = cnt[2:0] == 3'd7;

/**********************  cnt********************************/
always @(posedge clk_1m or negedge rst_n)
	if(~rst_n)
		cnt <= 9'd0;
	else if(~oe)
		cnt <= 9'd0;
	else if(~(active | active_check))
		cnt <= 9'd0;
	else if(cnt_clr | chk_cnt_clr)
		cnt <= 9'd0;
	else if(~dec_en)
		cnt <= {1'b0, (cnt[7:0] + 1'b1)};
	else 
		cnt <= cnt + 1'b1;

endmodule
